Fabricating integrated circuits with faster and/or an increasing number of semiconductor devices is a continuing trend in integrated circuit technology. A very influential factor in this trend is technology scaling, i.e., the reduction in transistor feature sizes. Technology scaling has enabled transistors to become smaller, thus allowing for more dense integrated circuits in terms of the number of transistors packed on a chip.
At virtually the same time that transistors are becoming smaller, chip sizes have been increasing in size. The chip size increase has, in turn, resulted in transistor driving capability decreases and interconnect parasitics increases. Accordingly, integrated circuits, such as, embedded memory circuits, mixed-mode/RF signal circuits, and System on a Chip (SOC) circuits, must be very carefully designed to meet future speed demands. Design issues which are very critical in the development of such circuits include, for example, transistor architecture. Specifically, careful gate design, transistor sizing, and other such feature parameters are extremely important in order to optimize transistor performance.
Spacers are commonly used in the fabrication of semiconductor devices and integrated circuits. The spacers may be used, for example, to control transistor gate size, source and drain regions placement or other features. Because variously sized transistors and other features are often required in a particular integrated circuit design, spacers of different widths must be utilized during the fabrication thereof.
Spacers of different widths are typically formed using conventional etching methods. These etching methods, unfortunately, may damage the thin, dielectric gate insulating layer and substrate. Accordingly, a new method is needed for forming spacers of varying width.